The present invention relates to electronic data processing, and more particularly concerns a data processing system having a tightly coupled main processor and coprocessor for executing different types of instructions in a single stream, in an overlapped manner.
It is sometimes convenient to provide a system having a fixed repertoire of instructions, and to enhance that repertoire by providing a coprocessor for performing the operations required by a second set of instructions. The most common example of this is the combination of a microprocessor with a coprocessor for performing floating-point operations. Other examples include coprocessors for performing graphics operations and text operations.
Usually the coprocessor is "tightly coupled" to the main processor. The main processor actually fetches all instructions and operands for both the main processor and the coprocessor. The coprocessor merely performs the operations required by the enhanced instructions, such as the addition, subtraction, multiplication, or division of floating-point operands fetched by the main processor. It is also common for the coprocessor to provide a "hold-off" signal back to the main processor; the main processor does not fetch--or at least does not begin to execute--a subsequent instruction of either type. Then, when the coprocessor has completely finished executing the current instruction, it releases the hold-off, signaling the main processor to begin the next instruction from the stream.
Such tightly-coupled processor/coprocessor pairs appear externally to be a single processor executing an enhanced instruction set. No performance increase occurs from this combination--usually, in fact, a penalty is incurred, because the instructions performed by the coprocessor tend to be lengthy and complex. No advantage is taken of the idle operational facilities of the main processor while the coprocessor is performing one of its operations.